CS 452/652 Fall 2019 - Lecture 10

start := clock;
loop N times:
  operation;
endloop;
stop := clock;

• loop execution (counter, branch) → if relevant, measure with nop
• concurrent workflow requires start/stop coordination
• warm-up period with non-regular performance
• sometimes: dummy side effects needed to keep optimizer from eliding experiment code

• fixed N - simple
• fixed run-time - predictable, but more difficult to set up and run

ARM 920T CPU Caches

• various caches
  • L1 instruction cache; L1 data cache
  • branch target cache (branch predictors)
  • TLB (page translation cache)
  • write buffer: mediate fast CPU ↔ slow RAM; coalesce writes
• ARM 920T caching modes (marked in page descriptor)
  0. non-cached, non-buffered → synchronous
  1. non-cached, buffered → ordered
  2. write-through, buffered → cache always clean
  3. write-back, buffered → most efficient
• default configuration
  • L1 caches separate (not unified)
  • no L2 cache?
  • no lockdown
  • regular memory in write-back mode
  • device memory in non-cached mode
  • RedBoot disables L1 caches during 'go' command

ARM 920T Cache Setup

• very flexible, but convoluted instructions
• here: CP register always p15, first opcode always 0

MCR{<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>}
MRC{<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>}

• <Rd> is used to read/write value: bits 2 & 12 control data & instruction cache

• <Rd> can be anything
• <opcode2> set to 0 to denote entire cache
• <CRm> set to c5: invalidate i-cache
• <CRm> set to c6: invalidate d-cache
• <CRm> set to c7: invalidate both caches
• <CRm> set to c10: clean d-cache
• <CRm> set to c14: clean & invalidate d-cache

• enabled → disable: clean d-cache
• enabled → enable: clean d-cache
• disabled → disable: nothing
• disabled → enable: depends on previous state
  • enabled → disable → enable
  • information in cache might be stale
  • invalidate d-cache before disable or before re-enable
  • must also invalidate i-cache to invalidate branch target cache