CS 452/652 Fall 2022 - Lecture 7

Documents

• Programmer's Guide (local copy)
• Architecture Reference Manual (local copy)

Timing Measurements

• duration of operation?
• first approximation:

  start = clock();
  operation();
  stop = clock();
  

  • overhead/duration of clock?
  • accuracy of clock?
  • variations in operation?
  • interference?
• inflate impact of operation:

  start = clock();
  loop N times:
    operation();
  endloop;
  stop = clock();
  

• compute average time and/or enhanced statistics
• potential overheads
  • loop execution (counter, branch) → if relevant, measure with nop
  • concurrent workflow requires start/stop coordination
  • warm-up period with non-regular performance
  • sometimes: dummy side effects needed to keep optimizer from eliding experiment code
• N must be large enough to mitigate impact of these overheads
• experiment duration?
  • fixed N - simple
  • fixed run-time - predictable, but more difficult to set up and run

Realtime Loop

• real-time with fixed period X
• naive approach

  loop:
    sleep(X);
    action();
  endloop;
  

  ... is not sufficient: errors in sleep(), duration of action()
• account for deviations from perfect timing:

  target = clock();
  loop:
    target += X;
    sleep(target - clock());
    action();
  endloop;
  

Optimization

Compiler Optimization

• code without side effects might be removed
• repetitions might be removed
• loops unrolled
• code reordered based on performance of microarchitecture
• compiler understands data dependencies in synchronous control flow
• C/C++ keyword "volatile"
  • tells compiler about unspecified side effects related to a variable or memory location
  • compiler avoids reordering around and removal of volatile accesses
  • example declaration of memory-mapped register

    int cloaddr = 0xFE000000 + 0x3000 + 0x04;
    volatile unsigned int* cloptr = (volatile unsigned int*)(cloaddr);
    unsigned int tval = *cloptr;
    

• goal is complete understanding of what we are doing ⇒ enable optimization!

Runtime/Hardware Optimization

• pipelining and out-of-order execution
• very important challenge in other areas!
• use one processor core → not relevant for CS 452/652

CPU Caches

• various caches (Reference, Section B2.7)
  • L1 instruction cache; L1 data cache; L2 unified/shared cache
  • branch target cache (branch predictors)
  • TLB (page translation cache)
  • write buffer: mediate fast CPU ↔ slow RAM; coalesce writes
• Memory modes: Device vs Normal
• Caching modes: Non-Cacheable, Write-Through, Write-Back

Cache Setup/Maintenance

• SCTLR_EL1 (Guide, Section 4.3)
  • I and C flags for instruction and data cache respectively
  • controls EL0 and EL1 for Normal mode
• Cache Maintanance: Guide, Section 11.5/11.6; Referece, Sections D17.2.26/33/34
  • cache instruction
  • enabled → disable: clean cache?
  • enabled → enable: clean cache?
  • disabled → disable: nothing
  • disabled → enable: depends on previous state
    • enabled → disable → enable
    • information in cache might be stale
    • invalidate cache before disable or before re-enable?
• experiment!