CS 452/652 Fall 2022 - Lecture 9

Documents

• BCM - Broadcom BCM2711 data sheet (local copy)
• GIC - Interrupt Controller (local copy)

Interrupts

Basics

• motivation: avoid overhead from continuous polling
• hardware delivers asynchronous notifications
  • kernel potentially notifies task(s)
• interrupt handling also presents overheads
  • direct: pipeline flush, handler execution
  • indirect: cache disturbance (CPU, TLB, branch predictors)
• high-rate of interrupts? use hybrid approach:
  • poll device and deliver event
  • only enable interrupt, if poll (or several polls) unsuccessful
  • disable interrupt after it is triggered
  • real-world example: Linux NAPI
• not strictly necessary for CS 452 kernel

Context Switch

• return-to-task: task → IRQ → task
  • simple: use IRQ stack for task's execution context
  • example: record clock tick for later processing
  • example: record event on one core for later processing on another core
  • but: not used in CS 452 kernel
• preemption: task → IRQ → kernel → (other) task
  • dedicated kernel stack per user task?
    • mode switch user/kernel: callee-owned registers on thread's kernel stack
    • deferred thread switch in kernel: caller-owned registers on thread's kernel stack
  • single kernel stack
    • all state is critical ⇒ (at least temporarily) push some info on kernel stack
    • obtain and save user execution state
• here: always preempt, i.e., append current task to ready-queue and re-schedule!

Interrupt Hardware

• interrupt propagation: Device → Interrupt Controller → CPU
  • interrupt raised by device
  • interrupt routed by controller
  • interrupt taken and processed by CPU
• "Legacy interrupt controller" (BCM Section 6.4) - not used here
• Interrupt Controller: GIC-400, which is an ARM GIC v2 (GIC Chapter 4)
• base address (BCM Section 6.5.1): 0xFF840000
• boot loader disables interrupts for EL1 (see DAIFSet special register)
• GIC startup configuration: all interrupts disabled
  • other default configuration works fine
• set up user spsr (pstate) to enable interrupts during user task execution
• GICD - GIC distributor: general configuration (offset 0x1000)
• GCCC - GIC core: per-core GIC interface (offset 0x2000)
• features for security, virtualization, nested interrupts, inter-processor communication, etc. - not used here

GIC Configuration

• GICD_ISENABLERn → enable interrupt delivery
• GICD_ITARGETSRn → route to Core 0
• GICC_IAR → retrieve and ack interrupt number
• GICC_EOIR → confirm interrupt processed
• interrupt numbers:
  • BCM Section 6.2.4, Table 102: VC interrupts, timer: 0-3
  • BCM Section 6.3, Figure 7: VC interrupts at 96-159

Interrupt Handler

• handler executes in EL1 mode with EL1 stack; interrupts should be disabled
• exception vector setup (see Lecture 4)
• fully transparent context switch vs. keep track of entry/exit
• different entry routines → use macros to avoid code duplication
  • See example in demo09. Take a look at the source assembler version or use objdump -d to look at the binary code.
  • handler.S - using assembler macros (similar to C preprocessor) to code uniform routine for svc- or irq-based kernel entr