MIPS Encoding Reference


Instruction Encodings

Each MIPS instruction is encoded in exactly one word (32 bits). There are three encoding formats.

Register Encoding

This encoding is used for instructions which do not require any immediate data. These instructions receive all their operands in registers. Additionally, certain of the bit shift instructions use this encoding; their operands are two registers and a 5-bit shift amount.

ooooooss sssttttt dddddaaa aaffffff
FieldWidthDescription
o6Instruction opcode. This is 000000 for instructions using this encoding.
s5First source register, in the range 0-31.
t5Second source register, in the range 0-31.
d5Destination register, in the range 0-31.
a5Shift amount, for shift instructions.
f6Function. Determines which operation is to be performed. Values for this field are documented in the tables at the bottom of this page.

Immediate Encoding

This encoding is used for instructions which require a 16-bit immediate operand. These instructions typically receive one operand in a register, another as an immediate value coded into the instruction itself, and place their results in a register. This encoding is also used for load, store, branch, and other instructions so the use of the fields is different in some cases.

Note that the "first" and "second" registers are not always in this order in the assembly language; see "Instruction Syntax" for details.

ooooooss sssttttt iiiiiiii iiiiiiii
FieldWidthDescription
o6Instruction opcode. Determines which operation is to be performed. Values for this field are documented in the tables at the bottom of this page.
s5First register, in the range 0-31.
t5Second register, in the range 0-31.
i16Immediate data. These 16 bits of immediate data are interpreted differently for different instructions. 2's-complement encoding is used to represent a number between -215 and 215-1.

Jump Encoding

This encoding is used for jump instructions, which require a 26-bit immediate offset. It is also used for the trap instruction.

ooooooii iiiiiiii iiiiiiii iiiiiiii
FieldWidthDescription
o6Instruction opcode. Determines which operation is to be performed. Values for this field are documented in the tables at the bottom of this page.
i26Immediate data. These 26 bits of immediate data are interpreted differently for different instructions. 2's-complement encoding is used to represent a number between -225 and 225-1.

Instruction Syntax

This is a table of all the different types of instruction as they appear in the assembly listing. Note that each syntax is associated with exactly one encoding which is used to encode all instructions which use that syntax.

EncodingSyntaxTemplateComments
Register ArithLogf $d, $s, $t
DivMultf $s, $t
Shiftf $d, $t, a
ShiftVf $d, $t, $s
JumpRf $s
MoveFromf $d
MoveTof $s
Immediate ArithLogIo $t, $s, i
LoadIo $t, immed32i is high or low 16 bits of immed32
Brancho $s, $t, labeli is calculated as (label - (current + 4)) >> 2
BranchZo $s, labeli is calculated as (label - (current + 4)) >> 2
LoadStoreo $t, i ($s)
Jump Jumpo labeli is calculated as (label - (current + 4)) >> 2
Trapo i

Opcode Table

These tables list all of the available operations in MIPS. For each instruction, the 6-bit opcode or function is shown. The syntax column indicates which syntax is used to write the instruction in assembly text files. Note that which syntax is used for an instruction also determines which encoding is to be used. Finally the operation column describes what the operation does in pseudo-Java plus some special notation as follows:

"MEM [a]:n" means the n bytes of memory starting with address a.
The address must always be aligned; that is, a must be divisible by n, which must be a power of 2.

"LB (x)" means the least significant 8 bits of the 32-bit location x.
"LH (x)" means the least significant 16 bits of the 32-bit location x.
"HH (x)" means the most significant 16 bits of the 32-bit location x.

"SE (x)" means the 32-bit quantity obtained by extending the value x on the left with its most significant bit.
"ZE (x)" means the 32-bit quantity obtained by extending the value x on the left with 0 bits.

Arithmetic and Logical Instructions
InstructionOpcode/FunctionSyntaxOperation
add 100000ArithLog $d = $s + $t
addu 100001ArithLog $d = $s + $t
addi 001000ArithLogI$t = $s + SE(i)
addiu 001001ArithLogI$t = $s + SE(i)
and 100100ArithLog $d = $s & $t
andi 001100ArithLogI$t = $s & ZE(i)
div 011010DivMult lo = $s / $t; hi = $s % $t
divu 011011DivMult lo = $s / $t; hi = $s % $t
mult 011000DivMult hi:lo = $s * $t
multu 011001DivMult hi:lo = $s * $t
nor 100111ArithLog $d = ~($s | $t)
or 100101ArithLog $d = $s | $t
ori 001101ArithLogI$t = $s | ZE(i)
sll 000000Shift $d = $t << a
sllv 000100ShiftV $d = $t << $s
sra 000011Shift $d = $t >> a
srav 000111ShiftV $d = $t >> $s
srl 000010Shift $d = $t >>> a
srlv 000110ShiftV $d = $t >>> $s
sub 100010ArithLog $d = $s - $t
subu 100011ArithLog $d = $s - $t
xor 100110ArithLog $d = $s ^ $t
xori 001110ArithLogI$d = $s ^ ZE(i)
Constant-Manipulating Instructions
InstructionOpcode/FunctionSyntaxOperation
lhi 011001LoadIHH ($t) = i
llo 011000LoadILH ($t) = i
Comparison Instructions
InstructionOpcode/FunctionSyntaxOperation
slt 101010ArithLog $d = ($s < $t)
sltu 101001ArithLog $d = ($s < $t)
slti 001010ArithLogI$t = ($s < SE(i))
sltiu 001001ArithLogI$t = ($s < SE(i))
Branch Instructions
InstructionOpcode/FunctionSyntaxOperation
beq 000100Branch if ($s == $t) pc += i << 2
bgtz 000111BranchZ if ($s > 0) pc += i << 2
blez 000110BranchZ if ($s <= 0) pc += i << 2
bne 000101Branch if ($s != $t) pc += i << 2
Jump Instructions
InstructionOpcode/FunctionSyntaxOperation
j 000010Jump pc += i << 2
jal 000011Jump $31 = pc; pc += i << 2
jalr 001001JumpR $31 = pc; pc = $s
jr 001000JumpR pc = $s
Load Instructions
InstructionOpcode/FunctionSyntaxOperation
lb 100000LoadStore$t = SE (MEM [$s + i]:1)
lbu 100100LoadStore$t = ZE (MEM [$s + i]:1)
lh 100001LoadStore$t = SE (MEM [$s + i]:2)
lhu 100101LoadStore$t = ZE (MEM [$s + i]:2)
lw 100011LoadStore$t = MEM [$s + i]:4
Store Instructions
InstructionOpcode/FunctionSyntaxOperation
sb 101000LoadStoreMEM [$s + i]:1 = LB ($t)
sh 101001LoadStoreMEM [$s + i]:2 = LH ($t)
sw 101011LoadStoreMEM [$s + i]:4 = $t
Data Movement Instructions
InstructionOpcode/FunctionSyntaxOperation
mfhi 010000MoveFrom $d = hi
mflo 010010MoveFrom $d = lo
mthi 010001MoveTo hi = $s
mtlo 010011MoveTo lo = $s
Exception and Interrupt Instructions
InstructionOpcode/FunctionSyntaxOperation
trap 011010TrapDependent on operating system; different values for immed26 specify different operations. See the list of traps for information on what the different trap codes do.

Opcode Map

ROOT

Table of opcodes for all instructions:

000001010011100101110111
000REGjjalbeqbneblezbgtz
001addiaddiusltisltiuandiorixori
010
011llolhitrap
100lblhlwlbulhu
101sbshsw
110
111

REG

Table of function codes for register-format instructions:

000001010011100101110111
000sllsrlsrasllvsrlvsrav
001jrjalr
010mfhimthimflomtlo
011multmultudivdivu
100addaddusubsubuandorxornor
101sltsltu
110
111

Campaign Waterloo

David R. Cheriton School of Computer Science
University of Waterloo
Waterloo, Ontario, Canada N2L 3G1

Tel: 519-888-4567 x33293
Fax: 519-885-1208

Contact | Feedback: cs-webmaster@cs.uwaterloo.ca | David R. Cheriton School of Computer Science | Faculty of Mathematics


Valid HTML 4.01!Valid CSS! Last modified: Monday, 23-Aug-2010 16:11:56 EDT


Menu:ShowHide